This invention relates to volatile memory elements for integrated circuits and, more particularly, to volatile memory elements with transistor body biases that are controlled during operation.
Integrated circuits such as programmable logic devices may contain volatile memory elements in the form of static random access memory (SRAM) cells. In programmable logic device integrated circuits, SRAM cells may serve as configuration random access memory (CRAM) cells. Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. CRAM cells are used to store configuration data supplied by the user. Once loaded, CRAM cells supply control signals to transistors to configure the transistors to implement the desired logic function.
Volatile memory elements such as SRAM and CRAM cells are typically based on cross-coupled inverters (latches). In each memory element, the cross-coupled inverters may be connected to an address transistor that is turned on when data is being read from or written into the memory element. When no data is being read from or written into the memory element, the address transistor is turned off to isolate the memory element. Cross-coupled inverters and address transistors can be formed from complementary metal-oxide-semiconductor (CMOS) transistors such as n-channel metal-oxide-semiconductor (NMOS) and p-channel metal-oxide-semiconductor (PMOS) transistors.
As semiconductor technology scales towards smaller sizes, lower power supply voltages may be used to power integrated circuits. Lower power supply voltages and smaller devices may lead to decreased read and write margins for volatile memory elements. This can pose challenges for reliable device operation.
It would therefore be desirable to be able to provide volatile memory cells that demonstrate improved read and write margins.